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INTEGRATED CIRCUITS
DATA SHEET
SAA4951 Memory controller
Preliminary specification File under Integrated Circuits, IC02 April 1994
Philips Semiconductors
Preliminary specification
Memory controller
FEATURES * Support for acquisition, display and deflection PLL * 50/100 (or 60/120) Hz scan conversion for different input data rates: 12, 13.5, 16 and 18 MHz * Support for 4:3 and 14:9 display on a 16:9 screen (horizontal compression) * Support for Y:U:V data rates of 4:1:1, 4:2:2, and 4:4:4 * Horizontal zoom * Still picture * Support for one or two field memories * Support for different video memory types like TMS 1050/60/70/2970 * Progressive scan * Programmable via microcontroller port * Golden Scart option * Support for Multi-PIP. QUICK REFERENCE DATA SYMBOL VDD IDD Tamb PARAMETER supply voltage supply current operating ambient temperature 4.5 - 0 MIN. 5.0 50 - TYP. 5.5 - +70 MAX. GENERAL DESCRIPTION
SAA4951
The memory controller SAA4951 has been designed for high end TV sets using 2fH-technics. The circuit provides all necessary write, read and clock pulses to control different field memory concepts. Furthermore the drive signals for the horizontal and vertical deflection power stages are generated. The device is connected to a microcontroller via an 8-bit data bus. The controller receives commands via the I2C-bus. Due to this fact the start and stop conditions of the main output control signals are programmable and the SAA4951 can be set in different function modes depending on the used TV-feature concept.
UNIT V mA C
ORDERING INFORMATION PACKAGE EXTENDED TYPE NUMBER SAA4951WP Note 1. SOT187-2; 1996 December 13. PINS 44 PIN POSITION PLCC MATERIAL plastic CODE SOT187(1)
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Philips Semiconductors
handbook, full pagewidth
Memory controller
Y 12 NORIC SAA4940 BENDIC SAA7158 VIDEO ENHANCEMENT Y/U/V LINEFLICKER REDUCTION DACs 12 12
LPY
MEMORY 1 1 x TMS4C2970 (3 x TMS4C1070)
U
LPU
A/D TDA8755 MEMORY 2 1 x TMS4C2970 (3 x TMS4C1070) 12 12 NOISE REDUCTION INCLUSIVE CROSSCOLOUR REDUCTION
V 2 12 12/13.5/16/18 MHz CONTROL 32/36 MHz 2
LPV
3
VCO1 H2, V2 (32 kHz/100 Hz) VCO2B 2 8 C-BUS 27 MHz MEMORY CONTROLLER SAA4951 VCO2 C PCB83C652 2
MGH131
VSYNC
SCI
I2C
Preliminary specification
SAA4951
Fig.1 Improved Picture Quality (IPQ) module.
Philips Semiconductors
Preliminary specification
Memory controller
PINNING SYMBOL HRD VDD SWC1 SRC SWC2 WEXT IE1 WE1 STROBE VDD HRA BLNA VSS LLA IE2 WE2 CLV ALDUV/VB RE1 RE2 BLND ALE WRD VDD VSS P0 P1 P2 P3 P4 P5 P6 P7 LLDFL VSS HRDFL 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 PIN 1 2 3 4 5 6 7 8 9 10 11 TYPE(1) O - O O O I O O I - O I - I O O O O O O O I I - - I I I I I I I/O I/O I - O positive supply voltage serial write clock, memory 1 serial read clock, memory 1 serial write clock, memory 2 external write enable input input enable signal, memory 1 write enable signal, memory 1 strobe function positive supply voltage horizontal reference signal, acquisition part horizontal blanking signal, acquisition part ground line-locked clock signal, acquisition part input enable signal, memory 2 write enable signal, memory 2 video clamping signal DESCRIPTION horizontal reference signal, display part
SAA4951
acquisition load signal, chrominance U, V / vertical blanking read enable signal, memory 1 read enable signal, memory 2 horizontal blanking signal, display part address latch enable signal write/read data signal positive supply voltage ground data input signal, (LSB = least significant bit) data input signal data input signal data input signal data input signal data input signal data input/output signal data input/output signal, (MSB = most significant bit) line-locked clock signal, deflection part ground horizontal reference signal, deflection part
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Philips Semiconductors
Preliminary specification
Memory controller
SAA4951
SYMBOL VDD HDFL VDFL VACQ TEST RSTW2 RSTW1 LLD VSS Note 1. I = Input O = Output
PIN 36 37 38 39 40 41 42 43 44
TYPE(1) - O O I I O O I - positive supply voltage
DESCRIPTION horizontal synchronization signal, deflection part vertical synchronization signal, deflection part vertical synchronization signal, acquisition part test input reset write signal, memory 2 reset write signal, memory 1 line-locked clock signal, display part ground
42 RSTW1
6 WEXT
5 SWC2
SWC1
IE1 7 WE1 8 STROBE 9 VDD 10 HRA/BLNA 11 VSS 12 LLA 13 IE2 14 WE2 15 CLV 16 ALDUV/VB 17
40 TEST
handbook, full pagewidth
41 RSTW2
SRC
1 HRD
2 VDD
44 VSS
43 LLD
4
3
39 VACQ 38 VDFL 37 HDFL 36 VDD 35 HRDFL
SAA4951WP
34 VSS 33 LLDFL 32 P7 31 P6 30 P5 29 P4
ALE 21
WRD 22
VDD 23
VSS 24
P2 27
P0 25
P1 26
BLND 20
RE1 18
RE2 19
P3 28
MGH129
Fig.2 Pin configuration.
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Philips Semiconductors
Preliminary specification
Memory controller
FUNCTIONAL DESCRIPTION Block diagram and short description The SAA4951 is a memory controller intended to be used for scan conversion in TV receivers. This conversion is done from 50 to 100 Hz or from 60 to 120 Hz. The device supports three separate PLL circuits: the acquisition PLL can run on 12, 13.5, 16 or 18 MHz, the display PLL on 27, 32 or 36 MHz, and the deflection PLL on 27 MHz. This allows frequency doubling for input data rates of 13.5, 16 and 18 MHz. For displaying a 4:3 picture on a 16:9 screen additional horizontal compression is possible when using the clock configuration 12/32 MHz and 13.5/36 MHz. The VCO and loop filter are peripheral parts of each PLL, the clock divider and generation of the reference pulse for the phase detector are internally provided. The device generates all write, read and clock pulses to operate a field memory in a desired mode. The required signals are programmable via an 8-bit parallel microcontroller port. The block diagram of the SAA4951 is shown in Fig.3. The clock signal from the VCO is fed in at pin 13, a horizontal reference pulse for the phase discriminator is fed out at pin 11. By setting the clock divider to different values the PLL can be forced to run on different clock frequencies. Besides this the acquisition part can also be configured to run on a fixed input clock. Then pin 11 is an input pin, so the horizontal reference pulse can be supplied from the outside. This mode is intended to be used together with a digital decoder which is providing clock and reference pulses. In the horizontal processing part the signals WE1, WE2 and CLV are generated. The vertical processing block supplies the signals RSTW1 and RSTW2 as well as enable signals for the horizontal part. The start and stop position of the pulses are programmable, the increment being 4 clock cycles in the horizontal part and 1 line in the vertical part. For WE1 and WE2 an additional 2-bit fine delay is available.
SAA4951
Display related control signals are derived from the display PLL. The functions are similar to the acquisition part. The PLL can be switched to 32 or 36 MHz, in case of 27 MHz this clock is taken from the deflection PLL which always runs on 27 MHz. In the horizontal part the pulse WE2, RE1, RE2 and BLN are programmable in increments of 4 clock cycles, each one adjustable by an additional 2-bit fine delay. The vertical processing block generates VDFL, RSTW2 and enable signals for the horizontal part. The deflection PLL runs on 27 MHz. From this clock the 16 kHz PLL reference pulse HRDFL is generated as well as the 32 kHz deflection pulse HDFL. In the vertical acquisition part the distance between the incoming 50 Hz vertical synchronization pulse VACQ and the horizontal synchronization pulse CLV generated by the horizontal deflection circuit is measured. In addition the field length is calculated by the acquisition counter, which is enabled by CLV. A fixed vertical reset pulse RSTW1 and a programmable vertical control of the write enable pulse WE1 for memory 1 defining the vertical write window are generated. In the display section the programmable 100 Hz write enable pulse WE2 for the memory 2 and the programmable 100 Hz read enable pulses RE1 and RE2 are provided. The 100 Hz vertical synchronizing signal VDFL is corrected by the calculated values of the acquisition part. The position of this pulse can also be chosen by the microcontroller. Furthermore two field identification signals for 50 Hz and for 100 Hz are generated internally to mark the corresponding fields by the microcontroller.
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Philips Semiconductors
Preliminary specification
Memory controller
SAA4951
handbook, full pagewidth
WEXT
6
17
ALDUV/VB SWC1 HRA/BLNA CLV
SAA4951
3 11
ACQ-CLOCK GENERATOR LLA 13
ACQ H-TIMING
16
VACQ STROBE ALE WRD P0 P1 P2 P3 P4 P5 P6 P7
39 9 21 22 ACQ V-TIMING
42
RSTW1
5 41 8 LOGIC MICROPROCESSORINTERFACE 15 7 14 DSP V-TIMING 38
SWC2 RSTW2 WE1 WE2 IE1 IE2 VDFL
25 26 27 28 29 30 31 32
20 DSP H-TIMING 18 19 1 4
BLND RE1 RE2 HRD SRC
LLD
43
DSP-CLOCK GENERATOR
37 LLDFL 33 DFL-CLOCK GENERATOR DFL TIMING
HDFL
35
HRDFL
MGH130
Fig.3 Block diagram.
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Philips Semiconductors
Preliminary specification
Memory controller
Microcontroller interface The SAA4951 is connected to a microcontroller via pins P0 to P7, ALE and WRD. This controller receives commands from the I2C-bus and sets the registers of the SAA4951 accordingly. Fig.4 shows the timing of these signals. Address and data are transmitted sequentially on the bus with the falling edge of ALE denoting a valid address and the falling edge of WRD indicating valid data. The individual registers, their address and their function are listed in Table 1. Various start and stop registers are
SAA4951
9 bits wide, in this case the MSB is combined with other MSBs or fine delay control bits in an extra register which has to be addressed and loaded separately. In order to load the proper values to the vertical write enable registers in case of median filtering, information about the current 100 Hz field is necessary. To obtain these data, the microcontroller sends the address 80Hex (READ mode) which puts the SAA4951 in output mode for the next address / data cycle. For this one cycle the WRD pin works as a RDN pin.
handbook, full pagewidth ALE
WRD
DATA
ADDRESS
DATA
ADDRESS
DATA
ADDRESS
MGH133
Fig.4 P-interface timing.
Table 1
Internal registers. REGISTER FUNCTION
ADDRESS (HEX)
Vertical pulses generated from the display clock 40 41 42 43 44 45 46 VDFLSTA VDFLSTO VWE2STA VWE2STO VRE2STA VRE2STO VDMSB start of VDFL pulse (lower 8 of 9 bits) end of VDFL pulse (lower 8 of 9 bits) start of vertical write enable (lower 8 of 9 bits) end of vertical write enable (lower 8 of 9 bits) start of vertical read enable (lower 8 of 9 bits) end of vertical write enable (lower 8 of 9 bits) bit 0: MSB of VDFLSTA bit 1: MSB of VDFLSTO bit 2: MSB of VWE2STA bit 3: MSB of VWE2STO bit 4: MSB of VRE1STA bit 5: MSB of VRE1STO
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Philips Semiconductors
Preliminary specification
Memory controller
SAA4951
ADDRESS (HEX)
REGISTER
FUNCTION
Horizontal pulses generated from the display clock 48 49 4A 4B 4C 4D 4E BLNDSTA BLNDSTO HWE2STA HWE2STO HRESTA HRESTO HDMSB start of horizontal blanking pulse (lower 8 of 9 bits) end of horizontal blanking pulse (lower 8 of 9 bits) start of horizontal write enable (lower 8 of 9 bits) end of horizontal write enable (lower 8 of 9 bits) start of horizontal read enable (lower 8 of 9 bits) end of horizontal read enable (lower 8 of 9 bits) bit 0: MSB of BLNDSTA bit 1: MSB of BLNDSTO bit 2: MSB of HWE2STA bit 3: MSB of HWE2STO bit 4: MSB of HRESTA bit 5: MSB of HRESTO 4F HDDEL bit 0: fine delay of BLND (LSB) bit 1: fine delay of BLND (MSB) bit 2: fine delay of HWE2 (LSB) bit 3: fine delay of HWE2 (MSB) bit 4: fine delay of HRE (LSB) bit 5: fine delay of HRE (MSB) Vertical pulses generated from the acquisition clock 50 51 52 VWE1STA VWE1STO VAMSB start of vertical write enable (lower 8 of 9 bits) end of vertical write enable (lower 8 of 9 bits) bit 0: MSB of VWE1STA bit 1: MSB of VWE1STO Horizontal pulses generated from the acquisition clock 58 59 5A 5B 5C CLVSTA CLVSTO HWE1STA HWE1STO HAMSBDEL start of CLV pulse end of CLV pulse start of horizontal write enable (lower 8 of 9 bits) end of horizontal write enable (lower 8 of 9 bits) bit 0: MSB of HWE1STA bit 1: MSB of HWE1STO bit 2: fine delay of HWE1 (LSB) bit 3: fine delay of HWE1 (MSB) bit 4: memory configuration bit 2 (MC2): 0 = 1050/60; 1 = 1070/2970 bit 5: WEXT (external WE) bit 6: SFR (select field recognition)
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Philips Semiconductors
Preliminary specification
Memory controller
SAA4951
ADDRESS (HEX)
REGISTER
FUNCTION
Registers to turn on different modes 60 61 80 MODE0 MODE1 READ mode register 0 mode register 1 the bits of the two mode registers define the operating mode of the SAA4951 read mode by sending this address the SAA4951 is switched to output mode for the next address/data cycle, i. e. the microcontroller reads data from the SAA4951 As it can be seen from the above table the registers form groups which are reflected in the addressing scheme according to Table 2. Table 2 Internal register addressing scheme. INTERNAL REGISTER ADDRESS RW 7 1 0 0 0 0 0 0 Note 1. X = don't care, D = data bit OP 6 X 0 1 1 1 1 1 MO 5 X X 1 0 0 0 0 AD 4 X X X 1 1 0 0 HV 3 X X X 1 0 1 0 D2 2 X X X D D D D D1 1 X X X D D D D D0 0 X X D D D D D microcontroller reads data all registers off select mode 1 / mode 2 select hor. ACQ registers select vert. ACQ registers select hor. DSP registers select vert. DSP registers
bit names:
RW OP MO AD HV D2 D1 D0
read/write bit: 1 = read, 0 = write operate bit, must be 1 to address any register mode bit, select mode registers select acquisition (= 1) or display (= 0) registers select horizontal (= 1) or vertical (= 0) registers data bit 2 data bit 1 data bit 0
The bits of the two mode registers control the operation modes.
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Philips Semiconductors
Preliminary specification
Memory controller
Table 3 Mode registers. BIT 0 (LSB) 1 2 3 NAME FSA0 FSA1 FSD0 FSD1 frequency select acquisition bit 0 frequency select acquisition bit 1 frequency select display bit 0 frequency select display bit 1 FSA1 0 0 1 1 FSD1 0 0 1 1 4 MODE0 5 FORMAT0 FORMAT1 FSA0 0 1 0 1 FSD0 0 1 0 1 27.0 MHz 27.0 MHz 32.0 MHz 36.0 MHz 12.0 MHz 13.5 MHz 16.0 MHz 18.0 MHz display frequency REMARKS
SAA4951
REGISTER MODE0
acquisition frequency
control bit 0 for data format control bit 1 for data format FORMAT1 0 0 1 1 FORMAT0 0 1 0 1 Y:U:V data rate 4: 1: 1 4: 2: 2 4: 4: 4 4: 4: 4
6 7 (MSB)
HDEL0 HDEL1
horizontal delay control bit 0 horizontal delay control bit 1 the bits HDEL0, HDEL1 control the position of the internal vertical read enable signals for RE1 HDEL1 0 0 1 1 HDEL0 0 1 0 1 2 lines earlier 1 line earlier normal 1 line later
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Philips Semiconductors
Preliminary specification
Memory controller
SAA4951
REGISTER MODE1 1 2 3 4 5 6 7
BIT 0 (LSB)
NAME DR STPWM1 STPWM2 MC1 GSC CCIR60 EXTLLA VFS display raster
REMARKS stop writing to memory 1: still picture mode stop writing to memory 2: still picture mode memory configuration bit 1 0: two field memories; 1: one field memory golden scart 0: normal IPQ mode; 1: golden scart input for external mode (13.5 MHz input clock) only: 0 = 50 Hz, 864 clock cycles per line; 1 = 60 Hz, 858 clock cycles per line horizontal reference pulse BLNA and clock LLA from external source 0: internal (PLL); 1: external vertical frequency select VFS 0 0 1 1 DR 0 1 0 1 display mode 100 Hz (312.5 lines) ABAB raster 100 Hz (313/312.5/312/312.5 lines) AABB raster 50 Hz (625 lines) 1:1, non-interlaced 50 Hz (1250 lines) 2:1, interlaced SWC1 The acquisition clock input signal LLA is connected through the memory controller circuit. LLA is internally buffered and put out as serial write clock SWC1 for the memory 1. Additionally SWC1 is used as a clock signal for the three AD-converters and for the formatter function. ALDUV/VB The output signal ALDUV (analog load for the chrominance signals U and V) controls the formation of the 8-bit digital data information of the chrominance signals U and V.
Description of acquisition part LLA This is the main input clock pulse for the acquisition side of the memory controller generated by an external PLL circuit. Depending on the chosen system application LLA runs on the different frequencies of 12/13.5/16/18 MHz. The PLL circuit is controlled by the analog burst key pulse ABK provided by an inserted synchronization circuit (i. e. TDA2579) and the horizontal reference signal HRA supplied by the SAA4951 circuit. WEXT External write enable input for digital colour decoder applications, where the write enable signal is generated by the digital colour decoder. This signal is simply sampled by LLA and fed out at WE1.
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Philips Semiconductors
Preliminary specification
Memory controller
SAA4951
handbook, full pagewidth LLA
HRA
ALDUV (format 4:1:1)
ALDUV (format 4:2:2)
ALDUV (format 4:4:4)
MGH134
Fig.5 Timing of the signal ALDUV.
In case of an external write enable signal WEXT this output provides a vertical blanking signal, which can be used to generate a sandcastle pulse. The settings for the blanking signal are done with the registers VWE1STA (falling edge) and VWE1STO (rising edge). CLV The horizontal video clamping output pulse is generated by the acquisition clock signal LLA and is used as clamp pulse for the incoming luminance and chrominance signals Y, U, V of the three analog to digital converters. The time reference of CLV is the LOW-to-HIGH transition of the HRA signal. HRA/BLNA The horizontal reference output pulse HRA operates on the two standards PAL and NTSC. In the PAL standard HRA has a frequency of 15.625 kHz and in the NTSC standard the frequency is 15.734 kHz. In both cases the duty cycle of this signal is 50%. When the memory controller circuit is operating in a digital environment, a horizontal reference signal BLNA and a suitable acquisition clock pulse have to be supplied from the external used circuits (i. e. SAA7151A, DMSD and SAA7157, CGC).
WE1 A HIGH level on this output pin enables picture data to be written to field memory 1. WE1 is a composite signal, which includes the horizontal write enable signal as well as the vertical one. It is possible to delay the horizontal timing of WE1 up to three LLA clock cycles. In case of an external write enable signal WEXT the horizontal and vertical settings and the delay control have no influence on WE1. WE1 operates at a vertical frequency of 50 Hz. When the progressive scan mode is activated, WE1 is disabled every second field. In still picture mode this signal is set to LOW level. IE1 This output signal is used as a data input enable for memory 1. A logic HIGH level on this output pin enables the data information to be written into field memory 1. Via signal IE1 the still picture function is controlled. When this mode is selected, IE1 is switched to LOW level. It is possible to disable the still picture mode with externally supplied STROBE pulses.
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Philips Semiconductors
Preliminary specification
Memory controller
SAA4951
handbook, full pagewidth
HRA
CLVr CLV CLVf WE1r WE1 WE1f
MGH135
Fig.6 Programmable horizontal acquisition signals.
Table 4
Horizontal programming range of CLV and WE1 (see also Fig.6). CLVr = (4Nr + 2) x LLA CLVf = (4Nf + 2) x LLA WE1r = (2Nr + 2) x LLA WE1f = (2Nf + 2) x LLA 0 Nr < 215 0 < Nf 215 0 Nr < 431 0 < Nf 431 0 Nr < 213 0 < Nf 213 0 Nr < 428 0 < Nf 428 0 Nr < 143 0 < Nf 143 0 Nr < 287 0 < Nf 287 0 Nr < 255 0 < Nf 255 0 Nr < 511 0 < Nf 511 0 Nr < 191 0 < Nf 191 0 Nr < 383 0 < Nf 383
13.5 MHz, 50 Hz
13.5 MHz, 60 Hz
CLVr = (4Nr + 2) x LLA CLVf = (4Nf + 2) x LLA WE1r = (2Nr + 2) x LLA WE1f = (2Nf + 2) x LLA
18 MHz
CLVr = (8Nr + 4) x LLA CLVf = (8Nf + 4) x LLA WE1r = (4Nr + 4) x LLA WE1f = (4Nf + 4) x LLA
16 MHz
CLVr = (4Nr + 2) x LLA CLVf = (4Nf + 2) x LLA WE1r = (2Nr + 2) x LLA WE1f = (2Nf + 2) x LLA
12 MHz
CLVr = (4Nr + 2) x LLA CLVf = (4Nf + 2) x LLA WE1r = (2Nr + 2) x LLA WE1f = (2Nf + 2) x LLA
Nr Nf
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Philips Semiconductors
Preliminary specification
Memory controller
VACQ This is the 50 Hz vertical synchronization input signal derived from a suitable vertical synchronization circuit (i. e. TDA2579). The LOW-to-HIGH transition of this pulse is the timing reference of all vertical control signals of the SAA4951. RSTW1
SAA4951
The reset write output pulse 1 starts the write address pointer of field memory 1. The RSTW1 signal is derived from the 50 Hz vertical acquisition pulse VACQ and has a pulse width of 64 s (PAL) (see Fig.7).
handbook, full pagewidth
VACQ VrWE1 WE1 VfWE1 RSTW1
MGH136
Fig.7 Vertical acquisition timing.
Table 5 50 Hz 60 Hz
Vertical programming range of WE1 (see also Fig.7). VrWE1 = Nr x Line VfWE1 = Nf x Line VrWE1 = Nr x Line VfWE1 = Nf x Line 1 Nr < 311 1 < Nf 311 1 Nr < 261 1 < Nf 261
Nr Nf STROBE The asynchronous active HIGH STROBE input controls the input enable signals IE1 and IE2 of the memory block in the still picture mode. Description of display part LLD The input signal LLD is the main line-locked clock for the display side of SAA4951 generated by an external PLL circuit. Depending on the chosen application, LLD runs on three different frequencies 12/32/36 MHz. The PLL circuit is controlled by the horizontal deflection drive output pulse HDFL and the horizontal reference output signal HRD supplied by the memory controller. SWC2 Depending on the chosen system mode the output pin SWC2 delivers either the serial acquisition clock signal LLA (PSC mode, 50 Hz) or the serial display clock pulse LLD (two field memories, 100 Hz) to write the data information into memory 2. SRC The display clock input signal LLD is connected through the memory controller. LLD is internally buffered and put out as serial read clock SRC for field memory 1. Additionally SRC is used as clock pulse for the noise reduction circuit NORIC and the backend circuit BENDIC. HRD The horizontal reference display pulse HRD has a duty cycle of 50% and a frequency of 32 kHz. HRD is the reference pulse for the horizontal timing of the control signals RE1, RE2, WE2 and BLND generated by the display circuit of SAA4951. April 1994 15
Philips Semiconductors
Preliminary specification
Memory controller
BLND The output signal BLND is a horizontal blanking pulse and is used for the peripheral circuits NORIC and BENDIC. A LOW level indicates the blanking interval, a HIGH level indicates valid data from the memories. It is possible to delay the horizontal timing of BLND up to three steps of LLD clock pulses. WE2
SAA4951
A HIGH level on this output pin enables picture data to be written to field memory 2. WE2 is a composite signal, which includes the horizontal write enable signal as well as the vertical one. The horizontal timing of WE2 can be delayed up to three steps of LLD clock pulses. The WE2 output signal is used in different modes. When two field memories are implemented in a serial structure, WE2 operates at a vertical frequency of 100 Hz. In case two field memories are connected in parallel, WE2 has a vertical frequency of 50 Hz. In the progressive scan mode the WE2 signal is disabled every second field.
handbook, full pagewidth
HRD
HDSPr HDSP HDSPf
MGH137
Fig.8 Programmable horizontal display signals (HDSP = BLN, WE2, RE1 or RE2).
Table 6
Horizontal programming range for display signals (HDSP = BLN, WE2, RE1 or RE2; see also Fig.8). HDSPr = (2Nr + 2) x LLD HDSPf = (2Nf + 2) x LLD HDSPr = (2Nr + 2) x LLD HDSPf = (2Nf + 2) x LLD HDSPr = (2Nr + 2) x LLD HDSPf = (2Nf + 2) x LLD HDSPr = (4Nr + 4) x LLD HDSPf = (4Nf + 4) x LLD HDSPr = (4Nr + 4) x LLD HDSPf = (4Nf + 4) x LLD 0 Nr < 431 0 < Nf 431 0 Nr < 428 0 < Nf 428 0 Nr < 511 0 < Nf 511 0 Nr < 287 0 < Nf 287 0 Nr < 285 0 < Nf 285
27 MHz, 50 Hz 27 MHz, 60 Hz 32 MHz 36 MHz, 50 Hz 36 MHz, 60 Hz
Nr Nf IE2 This output signal is used as data input enable for memory 2. A logic HIGH level on this output pin enables the data information to be written to field memory 2.
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Philips Semiconductors
Preliminary specification
Memory controller
RE1 The output RE1 is the read enable signal for field memory 1. A HIGH level enables the picture data to be read from the memory. RE1 is a composite signal and includes the horizontal read enable timing as well as the vertical timing. It is possible to delay the horizontal timing of RE1 up to three steps of LLD clock pulses. Furthermore the vertical timing can be set one or two lines before RE2 respectively one line after RE2 (median filtering, noise reduction mode). RE2
SAA4951
The output RE2 is the read enable signal for field memory 2. A HIGH level enables the picture data to be read from memory 2. RE2 is a composite signal and includes the horizontal read enable timing as well as the vertical timing. The horizontal timing of RE2 can be delayed up to three steps of LLD clock pulses.
handbook, full pagewidth
VACQ VDSPr VDSP VDSPf
RSTW2
MGH138
Fig.9 Vertical display timing (VDSP = VWE2, VRE1/2 or VDFL).
Table 7 50 Hz 60 Hz
Vertical programming range for display signals (VDSP = WE2, RE1 or RE2; see also Fig.9). VDSPr = Nr x Line VDSPf = Nf x Line VDSPr = Nr x Line VDSPf = Nf x Line 1 Nr < 311 1 < Nf 311 1 Nr < 261 1 < Nf 261
Nr Nf
RSTW2 The reset write output pulse 2 starts the write address pointer of field memory 2. There are two functions possible for this pin. If a serial structure of the memories is implemented, RSTW2 is a 100 Hz pulse; in progressive scan mode and with one field memory, RSTW2 is a 50 Hz pulse. The pulse duration of RSTW2 is 32 s (PAL).
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Philips Semiconductors
Preliminary specification
Memory controller
Description of deflection part LLDFL The input signal LLDFL is the main line-locked clock pulse for the deflection side of the memory controller generated by an external PLL circuit. The frequency of LLDFL is always 27 MHz and is independent of the chosen feature modes. The PLL circuit operates on the video clamping pulse CLV of the acquisition part and the horizontal reference signal HRDFL generated by the deflection side of SAA4951. HRDFL
SAA4951
This horizontal output signal is the reference pulse for the horizontal deflection drive signal HDFL. The duty cycle of HRDFL is 50% and the cycle time is 64 s (PAL). In case of golden scart mode the cycle time is reduced to 32 s. HDFL The output signal HDFL is aimed for driving the connected horizontal deflection circuit. HDFL has a cycle time of 32 s and a pulse width of 64 x LLDFL = 2.37 s
handbook, full pagewidth
864/858 x LLDFL (50/60 Hz)
HRDFL 432/429 x LLDFL (50/60 Hz) HDFL
64 x LLDFL
64 x LLDFL
MGH139
Fig.10 Horizontal deflection timing.
VDFL This is the vertical synchronization output signal generated by the acquisition side of SAA4951. The timing reference of VDFL is the LOW-to HIGH transition of the vertical acquisition input pulse VACQ. Normally VDFL has a pulse width of 2.5 x HDFL = 80 s and a cycle time of 100 Hz. In normal mode the memory controller operates with two field memories and 100 Hz interlace picture reproduction. When the system includes only one field memory it is necessary to activate the AABB mode. In the simple field repetition mode the first two and the last two 100 Hz fields are out one upon another
Description of control inputs/outputs ALE The address latch enable input signal ALE is provided by the microcontroller. A falling edge of ALE denotes a valid address. WRD This is the write/read enable control signal supplied by the microcontroller. The HIGH-to-LOW transition of WRD indicates valid data. P0 to P7 The SAA4951 is controlled by the bidirectional port bus P0.0 to P0.7 of a microcontroller. Address and data are transmitted sequentially on the bus. TEST The TEST input pin has to be connected to ground.
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Philips Semiconductors
Preliminary specification
Memory controller
Timing specification The internal delays of the output signals referred to the respective clock are given in Table 8.
SAA4951
handbook, full pagewidth
CLK
OUT
tPLH tPD
tPHL
MGH140
Fig.11 Timing diagram.
Table 8 Delay table. Conditions: VDD = +4.5 V; Tj =+70 C (worst case). CLK LLA LLD LLDFL SRC SWC1 SWC2 SRC SRC LLDFL LLDFL SWC1 SRC SRC SWC1 LLDFL SWC1 LLDFL LLA SWC1 SRC SRC SWC2 WE1 WE2 RE1 RE2 HDFL HRDFL HRA HRD BLND ALDUV VB CLV VDFL WE1(EXT) OUT LOAD (pF) 15 45 45 25 15 10 10 10 25 10 10 10 25 25 25 25 25 25 tPLH (ns) 6.4 11.2 11.9 3.2 15.9 8.0 7.0 7.2 12.8 11.9 6.5 5.6 7.4 11.5 28.2 8.3 24.6 18.1 tPHL (ns) - - - - 18.9 10.9 8.6 8.7 15.8 13.9 8.4 7.6 10.3 14.0 30.3 11.3 27.6 21.1 tPD (ns) 6.5 13.7 13.9 2.6 - - - - - - - - - - - - - -
April 1994
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Philips Semiconductors
Preliminary specification
Memory controller
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI Tamb Tstg supply voltage input voltage operating ambient temperature storage temperature PARAMETER -0.5 -0.5 0 -40 MIN. +6.0 VDD + 0.5 +70 +125 MAX.
SAA4951
UNIT V V C C
CHARACTERISTICS Recommended operating conditions SYMBOL VDD VI VO IDD Tamb Tj PARAMETER DC supply voltage DC input voltage DC output voltage supply current operating ambient temperature junction temperature 4.5 -0.5 -0.5 - 0 0 MIN. 5.0 - - 50 - - TYP. MAX. 5.5 VDD+0.5 VDD+0.5 - 70 140 V V V mA C C UNIT
DC Characteristics Tamb = +25 C SYMBOL PARAMETER MIN. vIH VIL VOH TTL-input HIGH level input voltage TTL-input LOW level input voltage HIGH level output voltage 4.4 5.4 3.1 VOL LOW level output voltage - 0.1 0.1 0.27 ILI Rpull input leakage current internal pull-up resistor for I/O cells - 42 35 1.0 150 105 A k V 2.0 2.0 - 0.8 0.8 - V V - MAX. V UNIT VDD (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 4.5 5.5 VDD or VSS - VIH or VIL VIH or VIL I0 = -2 A I0 = -2 A I0 = -4.0 mA/ 8.0 mA (SRC) I0 = +2 A I0 = +2 A I0 = -4.0 mA/ 8.0 mA (SRC) - - - - - TEST CONDITIONS VI (V) - OTHER
April 1994
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Philips Semiconductors
Preliminary specification
Memory controller
SAA4951
APPLICATION INFORMATION Fig.12 shows a block diagram of the application environment of the memory controller SAA4951. The full option chip set of the new TV-feature system (third generation) controlled by the I2C-bus includes the following circuits: TDA8709 TDA8755 TMS4C10XX TMS4C2970 SAA7158 SAA4940 SAA4951 83C652 3 x ADC (8-bit) with clamp and gain setting, 30 MHz or 1 x ADC 1 Mbit video RAM, (optional TMS4C1050/60/70) or 2.9 Mbit video RAM BENDIC (Back END IC) with LFR, CTI, Y-Peaking, DAC NORIC (NOise Reduction IC) with Noise Reduction (NR) and Cross Colour Reduction (CCR) Memory controller C software control of activated features
April 1994
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book, full pagewidth
CLV
SWC1
IE1
WE1
RSTW1
IE2
WE2
SWC2
RSTW2
SRC
BLND
RE1
ALE 21 16 22 MEMORY CONTROLLER 37 SAA4951 13 LLA HRD LLD 32/36 MHz CLV PD 27 MHz HRDFL LLDFL 12/13.5/16/ 18 MHz PD HDFL PD 1 43 35 33 LLDFL 27 MHz HDFL 25 to 32 9 39 11 HRA 38 VDFL 3 7 8 42 14 15 5 41 4 20 18 19
I2C
RE2
April 1994
RE1(1) NORIC SAA4940 24 6 x TMS4C1050/60/70 or 2 x TMS4C2970 LINEFLICKER REDUCTION DACs 24 VIDEO ENHANCEMENT 3 Y/U/V BENDIC SAA7158 RE2(1) MEMORY BLOCK
ADC
Philips Semiconductors
Y/U/V
12
3
TDA8755
Memory controller
(1)
NOISE REDUCTION INCLUSIVE CROSSCOLOUR REDUCTION
CLV
SWC1
RSTR
22
VCO VCO VCO
WRD
V DEFLECTION H
MICROCONTROLLER
P0 to P7
STROBE
VDFL
83C652
VACQ
STROBE
2
VACQ
ABK
COMP
MICROCONTROLLER-BUS
MGH132
(1) former: 3 x TDA8709 + external formatter
Preliminary specification
SAA4951
Fig.12 Application diagram.
Philips Semiconductors
Preliminary specification
Memory controller
PACKAGE OUTLINE PLCC44: plastic leaded chip carrier; 44 leads
SAA4951
SOT187-2
eD y X A ZE
eE
39
29 28
40
bp b1 wM
44
1
pin 1 index
E
HE A
e
A4 A1 (A 3)
k
6
18 k 1 Lp 7 e D HD 17 ZD B vMB detail X vM A
0
5 scale
10 mm
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT
mm
A
4.57 4.19
A1 min.
0.51
A3
0.25
A4 max.
3.05
bp
0.53 0.33
b1
0.81 0.66
D (1)
E (1)
e
eD
eE
HD
HE
k
k1 max.
0.51
Lp
1.44 1.02
v
0.18
w
0.18
y
0.10
Z D(1) Z E (1) max. max.
2.16 2.16
16.66 16.66 16.00 16.00 17.65 17.65 1.22 1.27 16.51 16.51 14.99 14.99 17.40 17.40 1.07
45 o
0.180 inches 0.020 0.01 0.165
0.630 0.630 0.695 0.695 0.048 0.057 0.021 0.032 0.656 0.656 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.12 0.590 0.590 0.685 0.685 0.042 0.040 0.013 0.026 0.650 0.650
Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION SOT187-2 REFERENCES IEC 112E10 JEDEC MO-047AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-25
April 1994
23
Philips Semiconductors
Preliminary specification
Memory controller
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all PLCC packages. The choice of heating method may be influenced by larger PLCC packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering
SAA4951
Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
April 1994
24
Philips Semiconductors
Preliminary specification
Memory controller
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA4951
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
April 1994
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